吳 昱徵

I'm currently a prospective graduate of Electrical engineering student at Chang Gung University with implementation experience in mixed-signal circuit design, including bandgap reference, PLL, DLL, and OTA. Skilled in circuit simulation using HSPICE , with experience in circuit analysis, noise evaluation, and performance optimization.

Familiar with digital design flow, including Verilog-based implementation digital circuit design and basic APR concepts. Interested in IC design roles involving circuit analysis, system integration, and high-performance design.

在學中曾學習過類比與數位電路設計，實作過IC設計課程，具備Full-Customed電路經驗。在類比電路方面，曾經實作過有關OTA、Band Gap Reference電路。具備類比電路的設計經驗。而專題曾經建立過鎖相迴路架構模擬(CPPLL)。

同時曾經參與過由記憶體學程方所舉辦之IC設計培訓營，在過程中學習有關於數位電路設計、Verilog 語言的編寫、合成、繞線的過程，並實作過數個小實驗。初步的理解從cell-based 角度出發的電路設計流程。

長庚電機系記憶學程說明會