Summary
Overview
Work History
Education
Skills
Timeline
Generic

Bin-Horn Fang

Software Engineer

Summary

My name is Philip. I currently work as a software engineer at Siemens EDA. My role involves Verification IP design, specifically focusing on CDSI and CDPHY VIP. I have a strong familiarity with systemverilog coding and UVM. In the past, I have successfully assisted customers in resolving various IP design issues.

Overview

3
3
years of professional experience
6
6
years of post-secondary education

Work History

Design Verification Engineer

Realtek Semiconductor
01.2024 - Current

Ethernet Macsec

1. Create inhouse bfm for 100g interface

2. Add preemption model in inhouse VIP

3. Add VLAN tag in inhouse VIP

MIPI CSI controller verification

1. Using Cadence Denali VIP to verify the DUT.

2. Building the UVM environment for verification

3. Integrate APB VIP to UVM testbench

4. Create scoreboard for CSI verificaiton

5. Create regression script

6. Random constraint verification

Software Engineer

Siemens EDA
02.2022 - 01.2024
  • Former Avery-Design Systems VIP Design Engineer
  • MIPI CDSI, CDPHY
  • Work duties:

1. Upgrade and enhance VIP:

- Upgrade dphy 3.0 to dphy 3.5

- Add assertions in the VIP

- Write compliance test cases

2. Providing assistance to five customers in RTL design verification. Solving over hundred problems from customers.

3. Verificate customer's CSI-2, DSI-2, CPHY and DPHY IP design according to the test plan provided by customer.

4. Using UVM to integrate the environment of customer DUT and our VIP.

International Scholar

IMEC
05.2021 - 12.2021

Using Python to accelerate the 3D neuron simulation.

Education

Master of Science - Nano Integration Electronic Circuit Engineer

National Cheng Kung University
Tainan
09.2019 - 01.2022

Bachelor of Science - Electrical Engineering

National Cheng Kung University
Tainan
09.2015 - 08.2019

Skills

    MIPI CDSI, CDPHY

Verification environment building

Test case writing

Simulator: Synopsis VCS, Cadence Xcelium, Siemens EDA Questasim

English communication

Familiar with linux operation

Timeline

Design Verification Engineer

Realtek Semiconductor
01.2024 - Current

Software Engineer

Siemens EDA
02.2022 - 01.2024

International Scholar

IMEC
05.2021 - 12.2021

Master of Science - Nano Integration Electronic Circuit Engineer

National Cheng Kung University
09.2019 - 01.2022

Bachelor of Science - Electrical Engineering

National Cheng Kung University
09.2015 - 08.2019
Bin-Horn FangSoftware Engineer