My name is Philip. I currently work as a software engineer at Siemens EDA. My role involves Verification IP design, specifically focusing on CDSI and CDPHY VIP. I have a strong familiarity with systemverilog coding and UVM. In the past, I have successfully assisted customers in resolving various IP design issues.
Ethernet Macsec
1. Create inhouse bfm for 100g interface
2. Add preemption model in inhouse VIP
3. Add VLAN tag in inhouse VIP
MIPI CSI controller verification
1. Using Cadence Denali VIP to verify the DUT.
2. Building the UVM environment for verification
3. Integrate APB VIP to UVM testbench
4. Create scoreboard for CSI verificaiton
5. Create regression script
6. Random constraint verification
1. Upgrade and enhance VIP:
- Upgrade dphy 3.0 to dphy 3.5
- Add assertions in the VIP
- Write compliance test cases
2. Providing assistance to five customers in RTL design verification. Solving over hundred problems from customers.
3. Verificate customer's CSI-2, DSI-2, CPHY and DPHY IP design according to the test plan provided by customer.
4. Using UVM to integrate the environment of customer DUT and our VIP.
Using Python to accelerate the 3D neuron simulation.
Verification environment building
Test case writing
Simulator: Synopsis VCS, Cadence Xcelium, Siemens EDA Questasim
English communication
Familiar with linux operation