Intern
- 三維積體電路設計法則發展部
- Chiplet routing with offset-via and teardrop
1. Hao-Ju Chang, Y.-H. Chen, H.-W. Huang, Y. Yeh, H.-M. Chen, and C.-N. J. Liu, “On awareness of offset-via and teardrop in advanced packaging interconnect synthesis,” in The 30th Asia and South Pacific Design Automation Conference Technical Program (ASP-DAC), pp. 774 –780, 2025.
2. Kang, Bo-Kai and Chang, Hao-Ju and Chen, Hung-Ming and Liu, Chien-Nan Jimmy, "ML/DL-Based Signal Integrity Optimization for InFO Routing." 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS). IEEE, 2024.
3. Chen, H. M., Ho, C. W., Wu, S. H., Lu, W., Huang, P. T., and Chang, Hao-Ju and Liu, C. N. J. "Reshaping System Design in 3D Integration: Perspectives and Challenges." Proceedings of the 2023 International Symposium on Physical Design (ISPD). 2023.
4. Chen, Yung-Chih, Hao-Ju Chang, and Li-Cheng Zheng. "Don’t-care-based node minimization for threshold logic networks." 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020.
5. 2020國際積體電 路電腦輔助設計(CAD) 軟體製作競賽」 定題組(A) 入選
2019國際積體電路電腦輔助設計(CAD) 軟體製作競賽 定題組(A) 入選
C Programming
Skilled in Python Programming
Machine Learning Model Development
Electronic design automation