Chen Po-Jiun

Project: USB Controller

• Performance Optimization: Successfully optimized the existing USB Controller RTL block by modifying the architecture/pipeline stages, leading to a [QUANTIFIABLE DATA]% increase in overall system throughput.
• Reliability Enhancement (ECC): Led the update and implementation of the Error Correction Code (ECC) engine, boosting the data correction capability by [QUANTIFIABLE DATA] levels/bits to reliably support high-density NAND Flash solutions.
• Research & RTL Modeling: Conducted an initial feasibility study on LDPC (Low-Density Parity-Check Code) technology for future ECC integration. Developed a functional LDPC model in Verilog to analyze implementation complexity and resource requirements, successfully demonstrating core encoding/decoding logic.
• Back-End Focus: Primarily responsible for the Controller-to-NAND Flash interface, performing RTL circuit block modification, optimization, and thorough verification to ensure robust interaction with the ONFI interface.

Main Components Involved:

• USB Protocol Controller • AXI Bus Interface • Flash (ONFI) • ECC • Randomizer