Cheng-Hung Lin (Wilson)

Over 9 years of experience in semiconductor industry with solid knowledge of assembly processes.

Expertise in 3DIC packaging and Flip Chip processes, including Die Attach, Flip Chip Bonding, Lid Attach(Heat Sink), Laser Marking, Ball Mount, thermal performance(Thermal Interface Materials) and high warpage control. Lead annual cost reduction projects to optimize manufacturing efficiency and reduce expenses.

As a R&D integration engineer on 3DIC technology, particularly focus on CoWoS technology with a strong fundamental investigations in 3DIC assembly processes, yield monitoring, SPC control and yield improvement. Additionally, I specialize in failure mode analysis(FA) and CoWoS Test Vehicle (TV) design. Beyond CoWoS, I have extensive knowledge of other packaging technologies, including SoIC and FCBGA. Besides my technical expertise, I possess strong communication and project coordination skills.

• Familiar with new device tape-out procedures in advanced package fab, including design rule checking, system building, BOM maintenance and material/chemical evaluation.
• Strong knowledge in advanced package process flow, including die to die joint, bumping and new generation on-substrate joint technology like LAB/TCB (laser assist bonding/thermal compression bonding).
• Cross-department cooperation experience with various departments including: Fab module/R&D/Manufacturing/PM/IT/QR/Material.
• Experienced in customer handling. Deliver customer’s voice to fab precisely and report manufacturing status appropriately to customer.
• Expert of die traceability system, including SoC, HBM, MLCC, InFO/CoWoS wafer and package form tracing.
• Won CIT (Continuous Improvement Team) competition with 3rd place in TSMC advanced package forum (2019).