

Dynamic digital IC designer with expertise in SystemVerilog and ARM architecture, previously at Mediatek. Achieved successful integration of low-power designs into flagship SoCs, enhancing performance and reliability. Skilled in static timing analysis and collaboration, driving innovative solutions in complex projects. Proven ability to optimize power and ensure design integrity.
Programming Languages: SystemVerilog
EDA Tools: Synopsys Design Compiler, PrimeTime
Architecture: ARM CPU Architecture (core design and bus protocols, eg, AXI/CHI)
Design Skills: Static Timing Analysis (STA), Low-power Design Techniques (UPF)