Summary
Overview
Work History
Education
Skills
Accomplishments
Patent and Publication
Timeline
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ChihChiang  Tsao

ChihChiang Tsao

Technical Manager

Summary

Over 8 years R&D module experience which focus on InFO and CoWoS advance 3D IC package process, chemical and tool development. Expertise in assembly, chip staking, flip chip bond, SMT process. Also involving in PKG level and Board level reliability verify and failure analysis. Earning most customer trust and mass production successful with InFO and CoWoS Package. Hope to lead a package team to resolving process and reliability issues with successful mass production. And also bring some innovation advance package ideas for company’s products value improvement.

Overview

9
9
years of professional experience
8
8
years of post-secondary education

Work History

3D IC Technical Manager

TSMC
Hsinchu
07.2020 - Current


  • Developed suggestions for technical process improvements to optimize resources.
  • Created, managed and integrated application interoperability while coordinating updates and developing test cases.
  • Guided, coached and lead project teams, delegating tasks and evaluating performance and progression of project pace.
  • Communicated cross-functionally with technology leaders across analysis, architecture, build, quality assurance, deployment and support teams on project execution.
  • Met with clients to gather and understand requirements and coordinated with system administrators and directors to plan and schedule project activities.
  • Designed, implemented and monitored integration between applications while coordinating updates and developing test cases.
  • Managed implementation of new technological improvements resulting in increased efficiency.

3D IC Principle Enginner

TSMC
Hsinchu
11.2014 - 06.2020
  • Reviewed plans, documents and related materials to assess projected actions and advise on changes.
  • Completed deep research into [Topic] to optimize related projects.
  • Created specialized staff teams for complex or new projects.
  • Inspected [Area] and recommended key updates.
  • Applied development best practices in daily tasks for efficiency and accuracy.
  • Calculated labor and material needs, making necessary orders and purchases.
  • Created detailed reports on engineering activities and findings.
  • Designed and implemented quality control processes to facilitate customer satisfaction.

Education

Ph.D. - Mechanical Engineering

National Yang Ming Chiao Tung University
Taiwan
07.2009 - 06.2013

Master of Science - Mechanical Engineering

National Yang Ming Chiao Tung University
Taiwan
09.2008 - 06.2009

Bachelor of Science - Mechanical And Electro-Mechanical Engineering

National Sun Yat-sen Universit
Taiwan
09.2004 - 06.2008

Skills

Process optimized by DOE method

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Accomplishments

  • Optimized the process method for t and define component warpage specification for solving high warpage component joint issue. (US patent)
  • Collaborated with team in the development of InFO SOW (Tesla Mojo ) and transfer to mass production successfully.
  • Delivering a novel component joint method for InFO SOW (Tesla Mojo ) solving high warpage wafer and component joint crack and RA fail issue.
  • Optimized process for solving DRAM stacking shift issue.

Patent and Publication

Patent

1. PACKAGE STRUCTURE. 2023, US-20230168451-A1 

2.  Fan-out packages and methods of forming the same.  2023, US-11664300-B2 

3. INTERCONNECTION JOINTS HAVING VARIABLE VOLUMES IN PACKAGE STRUCTURES AND METHODS OF FORMATION THEREOF . 2017, US 20170025382-A1.

4.  PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME. 2017,  US-20170317054-A1. 

5. Package structure and method for manufacturing the same. 2018,  US-9978716-B2.

6. STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE. 2018,US-20180315728-A1

7.  Structure and formation method of chip package with fan-out structure. 2019, US-10276536-B2 .

8.  PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF, 2019, US-20190139886-A1 .

9.  Integrated Fan-Out Packages and Methods of Forming the Same ,2019,  US-20190148262-A1 .

10. PACKAGE STRUCTURE WITH WARPAGE-CONTROL ELEMENT. 2019, US-20190252340-A1.

11. MANUFACTURING METHOD OF PACKAGE ON PACKAGE STRUCTURE.2020, US-20200006308-A1

12. INTEGRATED FAN-OUT PACKAGES WITH EMBEDDED HEAT DISSIPATION STRUCTURE. 2020,US-20200006191-A1 

13. Manufacturing method of package on package structure ,2020 ,US-10535644-B1 

14. PACKAGE STRUCTURE .2020, US-20200271873-A1 .

15. FORMATION METHOD OF PACKAGE STRUCTURE WITH WARPAGE-CONTROL ELEMENT.2020, US-20200279823-A1.

16. WORKPIECE HOLDER, WAFER CHUCK, WAFER HOLDING METHOD . 2021, US-20210225684-A1

17. Manufacturing method of package on package structure,2022, US-11342321-B2 .

18. Package structure with porous conductive structure and manufacturing method thereof . 2022, .US-11482491-B2      


Publication

1. Force sensor design and measurement for endodontic therapy. IEEE SENSORS JOURNAL VOL.1. NO.7, JULY 2013

2. Study on bending behavior of nickel-titanium rotary endodontic instruments by analytical and numerical analyses. International Endodontic Journal, 46, 379-388,2013


Timeline

3D IC Technical Manager

TSMC
07.2020 - Current

3D IC Principle Enginner

TSMC
11.2014 - 06.2020

Ph.D. - Mechanical Engineering

National Yang Ming Chiao Tung University
07.2009 - 06.2013

Master of Science - Mechanical Engineering

National Yang Ming Chiao Tung University
09.2008 - 06.2009

Bachelor of Science - Mechanical And Electro-Mechanical Engineering

National Sun Yat-sen Universit
09.2004 - 06.2008
ChihChiang TsaoTechnical Manager