Ching-Ho Lin

• Manger a three People High Speed Interface team
• Developed LVDS RX PHY (New IP) in Bridge IC

- 20M~140MHz CLK Rate ,140M~980Mb/s Data Rate

• Developed LVDS TX PHY (New IP) in Bridge IC

- 20M~140MHz CLK Rate ,140M~980Mb/s Data Rate

• Developed EDP RX PHY (New IP) in TEST IC

- Main Link 1.62G~5.4Gbps Data Rate EDP RX PHY Design

- Main Link and AUX With AC Coupling and CTLE PHY Design

• Developed Clock Embedded Differential Signaling(CEDS) Design(New IP)

-500M~2Gb/s Data Rate CDR PHY and PLL Design for CEDS

- High Speed Interface IP Integration

• Mobile LCD Driver Analog IP Designer

- 1.2Gb/s MIPI RX D-PHY Design

- Power IP(BGP/LDO) Design and Integration

• Bridge IC Analog IP Designer

- 1.5Gb/s MIPI RX D-PHY Design

- Developed VCS COSIM Flow for MIPI

• Integrated Power IP in mobile LCD driver(TDDI)

- Robust Power design flow

- BGP ,LV/MV Regulator and Current Generator Design