Ching Shun Hsu
Digital IC Design Engineer
Hsinchu County
Summary
Assistant Technical Manager with 10+ years experience of DFT hardware design at Novatek Microelectronic. Participated in the introduction of Novatek most advanced DFT technology, including core wrapper technology for large-scale IC & Siemens SSN + ISTC technology for 3D SoC. Also experienced in back-end flow for various projects.
Overview
15
15
years of professional experience
Work History
Assistant Technical Manager
Novatek Microelectronic
Hsinchu, Hsinchu
03.2011 - Current
- DFT hardware architecture manager for Novatek first 3D SoC (2024-2025)
- DFT hardware architecture manager for Novatek first 8K120 flagship TV SoC (2022-2023)
- DFT hardware design (10+ years)
- back-end flow manager (3 projects)
- back-end design (10+ years)
- digital IP design (10+ years)
Education
Master of Science - Electronics Engineering
National Yang Ming Chiao Tung University
Hsinchu, Taiwan 04.2001 -
Skills
RTL coding
FPGA verification
NC/VCS simulation
TCL script
C shell script
Timeline
Assistant Technical Manager
Novatek Microelectronic
03.2011 - Current
Master of Science - Electronics Engineering
National Yang Ming Chiao Tung University
04.2001 -
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