ChengWei Chu

• Develop more than 5 major new ISP IPs for sensor products

Review the C model and documents for the new IP algorithm to define the hardware architecture. Implement the RTL design and completely verify its function with an accurate bit-true C model using random tests.

• Collaborate with the project team to incorporate at least 4 existing IPs into more than 10 new sensor products.
• Front-end/Back-end EDA tools support.

• I was responsible for developing and validating several new functions of the RICA (Reconfigurable Instruction Cell Array) core.
• In charge of modifying and maintaining several stages of the frontend implementation flow of RICA core IP, especially to upgrade DFT and ATPG flow for partition of power domains.

• In charge of developing and implementing the digital design of touch controller ICs.
• Responsible for top-level integration of touch controller ICs. Preparing the FPGA environment for digital function emulation.
• Run frontend and backend tools/flows, including lint check (Spyglass), Synthesis (DC), DFT, ATPG, LEC, STA STA timing closure, and ECO.
• Support the SA/FW team to resolve MP issues.

• Integrate, design, and implement an image signal processor (ISP) on a Xilinx FPGA platform for surveillance camera products.
• Evaluate and verify the ISP functions of the FPGA platform on EVB boards or mass-produced PCB boards.
• Support less experienced team members in deciding the block architecture and advise about block implementation
• Collaborate with the algorithm team to develop the architecture of the ISP image pipeline. And evaluate the hardware cost of ISP sub-blocks and provide opinions based on the perspective of hardware implementation to improve the feasibility of the algorithm.

• Integrate the top-level of an ASIC development project.
• Emulate whole chip design on the FPGA platform.
• Support less experienced team members in deciding the block architecture and advise about block implementation