Da-Wei, Huang (David)

My research focuses on VLSI physical design automation, particularly detailed placement for advanced process nodes. I develop optimization algorithms that improve design quality, scalability, and efficiency, with applications to manufacturability-aware placement, GPU acceleration, and emerging cell architectures.

• (ICCAD’23) “Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations”
• (TODAES’25) “Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs”
• (DAC’25) “MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution”
• (ICCAD’25) “Generalized GPU-Accelerated Dynamic Programming with Application to Mixed-Cell-Height Detailed Placement”

• NSTC Graduate Research Fellowship Pilot Program
• Synopsys Ph.D. Talent Cultivation Scholarship
• 2023 The Phi Tau Phi Scholastic Honor Society of the Republic of China
• National Intercollegiate Athletic Games (Badminton)
• 2025 Badminton, men's group tournament, the second
• 2016 World Junior Championship Taiwan Team
• 2014 Badminton Asia Championships Taiwan Team