Summer Intern
Mentor Graphics (Siemens EDA)
07.2022 - 08.2022

My research focuses on VLSI physical design automation, particularly legalization and detailed placement for advanced process nodes. I develop optimization algorithms that improve design quality, scalability, and efficiency, with applications to manufacturability-aware placement, GPU acceleration, and emerging cell architectures.
Programming Language: C, Verilog, Python, and CUDA
Operating System: Linux
EDA Tool & Courses: Design Compiler, Innovus, Quantum Computer Engineering (TSRI course), and Cell-Based IC Physical Design and Verification with IC Compiler II (TSRI course)
English: TOEIC (740/990)