Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Generic
以隆 蔡

以隆 蔡

Analog IC Design Engineer
Hsinchu

Summary

Dynamic Analog Design Engineer with expertise in Hspice and Cadence, previously at Canyon.

Proven track record in designing compliant analog modules and enhancing product competitiveness through strategic analysis.

Strong collaborator skilled in cross-functional teamwork, driving process improvements, and achieving quality targets in semiconductor processes.

Overview

6
6
years of professional experience
2
2
Languages

Work History

Analog Design Engineer

Canyon
09.2023 - Current
  • 電路設計方面:設計與整合核心類比模組,包括 Bandgap Reference、LDO、BMC Transmitter/Receiver、USB PHY 以及 VBUS 檢測與控制電路,確保整體系統符合 USB-IF 所規範的 PD3.0/3.1 標準。
  • 功能整合與對齊市場競爭:分析競爭對手產品特性,規劃具市場競爭力之架構,達成功能對齊與差異化。
  • 實體設計:負責 Floor Plan 與 Layout 初步規劃,並與 Layout 工程師合作,進行 Power Routing、信號完整性與敏感模組的相對配置優化,確保整體晶片性能與製造可行性。
  • 跨部門合作:與 FW、數位設計與驗證工程師協作,討論模組介面與測試需求,確保系統整合順利。
  • Circuit Design:
    Designed and integrated key analog modules including Bandgap Reference, LDO, BMC Transmitter/Receiver, USB PHY, and VBUS detection and control circuits to ensure full compliance with USB-IF PD3.0/3.1 standards.
  • Feature Integration & Competitor Analysis:
    Analyzed competitor product features and planned a competitive architecture to achieve both functional alignment and differentiation.
  • Physical Design:
    Responsible for initial floor planning and layout strategy; collaborated with layout engineers on power routing, signal integrity, and optimal placement of sensitive modules to ensure overall chip performance and manufacturability.
  • Cross-Functional Collaboration:
    Worked closely with firmware, digital design, and verification teams to define module interfaces and testing requirements, ensuring smooth system integration.

Process Integration Engineer

Kinsus
06.2019 - 08.2023
  • 載板製程整合:熟悉 BT、ABF 載板製程,包括黃光(Photolithography)、蝕刻(Etching)、壓合等製程環節,能有效整合多項製程以達到品質與良率目標。
  • 跨部門協作:作為製程窗口,協調各製程單位與品保、製造、設備等團隊合作,處理良率異常與製程改善。
  • 製程異常分析:擅長使用 SEM、X-ray、切片等工具進行缺陷分析與根因追蹤,並提出有效改善對策。
  • Substrate Process Integration:
    Familiar with BT and ABF substrate processes, including photolithography, etching, and lamination. Capable of effectively integrating multiple process steps to achieve quality and yield targets.
  • Cross-Functional Collaboration:
    Served as the process integration interface, coordinating with process, quality assurance, manufacturing, and equipment teams to resolve yield issues and drive process improvements.
  • Failure Analysis and Troubleshooting:
    Skilled in using SEM, X-ray, and cross-section analysis tools for defect diagnosis and root cause identification, followed by the implementation of effective corrective actions.

Education

Master of Science - Degree Program of Electrical And Computer Engineer

National Yang Ming Chiao Tung University
Hsinchu
04.2001 -

University Degree - Department of Electronic Engineering

National Kaohsiung First University of Science And
Kaohsiung
04.2001 -

Skills

Hspice

Cadence

Analog circuit design

Simplis

Laker

Semiconductor process

Accomplishments

書卷獎(國立陽明交通大學)

獲頒於在學期間表現優異,成績名列前茅。


台灣半導體研究中心|結業證書

完成 21 小時「晶片設計課程-Logic Synthesis with Design Compiler(Lab: ADFP – TSMC 16nm)」訓練,涵蓋先進製程與邏輯綜合技術。(2024年8月)


Dean’s List Award – National Yang Ming Chiao Tung University
Awarded for outstanding academic performance and ranking among the top of the class during graduate studies.

Certificate of Completion – Taiwan Semiconductor Research Institute
Completed a 21-hour chip design course: Logic Synthesis with Design Compiler (Lab: ADFP – TSMC 16nm), covering advanced process technology and synthesis methodology. (August 2024)

Timeline

Analog Design Engineer

Canyon
09.2023 - Current

Process Integration Engineer

Kinsus
06.2019 - 08.2023

Master of Science - Degree Program of Electrical And Computer Engineer

National Yang Ming Chiao Tung University
04.2001 -

University Degree - Department of Electronic Engineering

National Kaohsiung First University of Science And
04.2001 -
以隆 Analog IC Design Engineer