Dynamic Analog Design Engineer with expertise in Hspice and Cadence, previously at Canyon.
Proven track record in designing compliant analog modules and enhancing product competitiveness through strategic analysis.
Strong collaborator skilled in cross-functional teamwork, driving process improvements, and achieving quality targets in semiconductor processes.
Hspice
Cadence
Analog circuit design
Simplis
Laker
Semiconductor process
書卷獎(國立陽明交通大學)
獲頒於在學期間表現優異,成績名列前茅。
台灣半導體研究中心|結業證書
完成 21 小時「晶片設計課程-Logic Synthesis with Design Compiler(Lab: ADFP – TSMC 16nm)」訓練,涵蓋先進製程與邏輯綜合技術。(2024年8月)
Dean’s List Award – National Yang Ming Chiao Tung University
Awarded for outstanding academic performance and ranking among the top of the class during graduate studies.
Certificate of Completion – Taiwan Semiconductor Research Institute
Completed a 21-hour chip design course: Logic Synthesis with Design Compiler (Lab: ADFP – TSMC 16nm), covering advanced process technology and synthesis methodology. (August 2024)