Specializing in signal integrity and power integrity for Mobile,AI,automotive chips. Proven expertise in high-speed interface simulation and collaborative design with cross-functional teams. Proficient in SIPI simulation,system concept, demonstrating strong problem-solving skills to drive project success.
Job Functions:
SI/PI (Signal integrity/power integrity)
5nm Automotive electronics SIPI – DDR5 5600Mbps/6400Mbps/7200Mbps , CSI/DSI-DPHY 4.5Gbps,CSI/DSI-CPHY 6Gsps/8Gsps SIPI simulation
Job Functions:
SI/PI (Signal integrity/power integrity)
■ 5nm MPW SIPI – DDR5 1DPC/2DPC DQ/CA(RCD) 5600Mbps/6400Mbps/7200Mbps simulation
■ 5nm MPW SIPI –D2D 56Gbps-NRZ simulation
Hspice , Spectre , HFSS , SIwave , Icepak , Clarity , PowerSI, ADS , SystemSI , SPIsim …
Job Functions:
SI/PI (Signal integrity/power integrity/de-sense)
■ 7nm MPW SIPI - TSMC GPIO (200MHz) , Silicon Creations LVDS(2Gbps) I/O
■ 7nm project Explorer SIPI - SDIO, MIPI-CDPHY , NPU performance - SDIO-SDR104(PKG noshield, PCB two-shield
design rule) , MIPI-CDPHY (DPHY-2.5Gbps,CPHY-3.5Gsps,4.5Gsps,PKG noshield,PCB 1.5x design rule,CTLE gain table) , NPU system level Power
Integrity with Idle to Max current profile , interference between LP4X and MIPI RX evaluation
■ 4nm MPW MPC4B CSI/DSI-DPHY 4.5Gbps,CSI/DSI-CPHY 6Gsps SIPI (CSI NS/EW compatible routing perfomance. DSI EW simulation ,DSI-EW, DSI/CSI AVDD_0p75 /DVDD_0p75/ pkg power merge suggestion
■ 4nm project Z3 SIPI -optimized InFO/FCCSP package routing, CSI-CPHY 3.5Gsps/4.5Gsps/6Gsps CTLE gain table setting. DSI 3.5Gsps TXEQ setting. GPIO IBIS model creation ,DSI CPHY(3.5Gsps)/DPHY(4.5Gbps) IBIS-AMI model creation and ADS verification ,CSI CPHY(4.5Gsps/6Gsps) IBIS model ADS CTLE pole-zero verification , interference between LP4X and MIPI RX evaluation
■ 3nm MPW SIPI - CSI/DSI-DPHY 4.5Gbps, CSI/DSI-CPHY 8Gsps (MIPI_C_PHY_specification_v2.0 & MIPI_D_PHY_specification_v2.5), DSI+CSI loopback SIPI simulation
SI/PI (Signal integrity/power integrity/de-sense)
■ Co-work with DDR3,DDR4,LPDDR3,LPDDR4,LPDDR4x IO designer to define DDR IO design spec
■ Package routing rule design for high speed interface (DDR, LVDS, SD ,eMMC, MIPI)
■ PCB routing rule design for high speed interface (DDR, LVDS, SD, eMMC, MIPI)
■ High speed interface SIPI simulation (DDR, LVDS, SD, eMMC, MIPI)
■ thermal simulation
Job Functions:
SI/PI (Signal integrity/power integrity/de-sense)
■ Co-work with LPDDR3,LPDDR4,LPDDR4x IO designer to define DDR IO design spec
■ Package routing rule design for high speed interface (DDR, LVDS, SD ,eMMC, MIPI)
■ PCB routing rule design for high speed interface (DDR, LVDS, SD, eMMC, MIPI)
■ High speed interface SIPI simulation (DDR, LVDS, SD, eMMC, MIPI)
■ CPU/GPU PI simulation
■ De-sense simulation/improvement of SIP (GPS, FM, BT, WiFi ,DDR, SD, eMMC, MIPI, LVDS)
Job Functions:
■ System design of RF/Baseband GSM/SWCDMA/LTE handset/tablet/module including GPS, Bluetooth, FM, WiFi subsystems
■ coordinate Antenna/HW/SW/factory
■ system De-sense simulation/measurement of mobile phone/tablet (GPS, FM, BT, WiFi ,2G/3G/4G)
Job Functions:
■ System design of RF/Baseband GSM/GPRS handset including GPS, Bluetooth, FM, WiFi subsystems
■ System integration of GSM RF IC
■ coordinate Antenna/HW/SW/factory
■ system De-sense simulation/measurement of mobile phone (GPS, FM, BT, WiFi ,2G)
Job Functions:
■ 3G ,3.5G feature phone development to include Qualcomm QSC6270/RTR6285,MSM6290 platform
■ Patent:
1.無線通訊裝置(wireless communication Apparatus), 2009, TW201037984 A1
2. 无线通信装置(wireless communication Apparatus).PEGATRON corp. Oct, 13 2010: application no. CN 200910134146.4 publication no. CN101860375
Job Functions:
■ 2.75G feature phone development to include MTK 62XX platform.
■ Dual mode (PHS/GSM) phone development
Dual network(GSM/WiFi VOIP) phone development
Job Functions:
■ BT/WiFi module design in with LTCC
■ BT product (headset, dangle)design
■ Technical training and transfer
■ Conference Paper
S.-J Chung, T.-C. Chou, and Y.-N Chiu, “A novel card-type transponder designed using retrodirective antenna array,” in IEEE MTT-S Int. Microwave Symp. Dig., pp.1123-1126, 2001
SI/PI (Signal integrity/power integrity/de-sense) DDR3,DDR4,LPDDR3,LPDDR4,LPDDR4x, DDR5 ,CSI/DSI-DPHY,CSI/DSI-CPHY,D2D
Familiar with tools ■Hspice , Spectre , HFSS , SIwave , Icepak , Clarity , PowerSI, ADS , SystemSI , SPIsim …
Co-work with IP designer , PKG designer ,PCB designer
IO characteristic check, IBIS IBIS-AMI modeling,RDL/metal/bump design, SI/PI model extraction,full interconnection simulation/correlation