
Hi, my name is Lin Guanxun.
I graduated from the Department of Electronic Engineering of the National Taiwan University of Science and Technology with a bachelor's degree. Since I have found interest in work, I am currently studying for a master's degree in the Department of Communications of the National Central University and am expected to graduate next year.
Currently, he is still working in MLT ,and has 5 years of experience as an FPGA engineer. Including basic training in the company, transferred from a hardware engineer to the system department as an FPGA engineer.
At the company, I participated in multiple projects, including wireless communication system development and radar development. In these projects, I was responsible for writing hardware description languages to the system and designing FPGA peripheral hardware circuits. I applied FPGA technology to repeater to achieve field application and functional optimization, and through the use of Xilinx Vivado With FPGA development tools such as Altera Quartus, VHDL and Verilog hardware description languages can be customized to achieve the functions required by customers. In recent years, as the communications market has been constantly updating products for other systems, FPGA has faced more challenges in product development. Currently, through the mutual cooperation between FPGA and embedded, complex systems have been successfully implemented in several projects of the company. Integrate software and hardware, and work with PCB Layout engineers to optimize product performance
1. Using Xilinx and Quartus in the repeater system core" FPGA and ADI RFIC " to detect LTE/NR IQ signal and perform corresponding signal processing( DDC / DUC / Single rate Filter Designed / Signal Clipping / AGC / ALC / DPD / OFDM ( FFT / IFFT) )
2.Familiar with repeaters in 3GPP specifications and design related performance
3. Use kintex 7 (7k70T/7k160T) or Zynq UltraScale+ MPSoC to verify the peripheral hardware circuit design, and also need to understand the hardware circuit design (UART/PHY/EEPROM/Fiber Optic/DDR4/DDR5 / RF(Mixer/ LNA/HPA) )
4. Optimizing FPGA design to ensure the best balance of performance and resource utilization thus involves timing/area analysis and constraints, the possibility of performance optimization on DSP to meet end customer requirements
5. Understand the operation and interface (DDR / JESD204B) of ADI RFIC (AD9361 / AD9371 /ADRV9009) and implementation in FPGA
6. Understand Adaptive filter theory and implenment in FPGA to let Repeater more convenient to use in the field.
1.Using Xilinx and Quartus in the repeater system core" FPGA and ADI RFIC " to detect LTE/NR IQ signal and perform corresponding signal processing( DDC / DUC / Single rate Filter Designed / Signal Clipping / AGC / ALC / DPD / OFDM ( FFT / IFFT) )
2.Familiar with repeaters in 3GPP specifications and design related performance
3. Use kintex 7 (7k70T/7k160T) or Zynq UltraScale+ MPSoC to verify the peripheral hardware circuit design, and also need to understand the hardware circuit design (UART/PHY/EEPROM/Fiber Optic/DDR4/DDR5 / RF(Mixer/ LNA/HPA) )
4. Conducted projects and performance presentations to clients and company executives.
5. Performed preventive maintenance and calibration of equipment and systems.
Linux
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