Accomplished Senior Pixel Engineer from EgisTec, adept in pixel layout design and TCAD simulation, significantly improved CP yield to over 95% and reduced the pixel photo layer. Expertise in semiconductor physics, complemented by strong teamwork abilities and effective project schedule control.
1. N3 process improvement
2. Transistor Device performance analysis & improvement
3. Transistor mismatch performance analysis & improvement
1. Fab 1 Dtof SPAD pixel design
a. SPAD pixel layout design
b. SPAD pixel process simulation
c. SPAD pixel DC simulation (Vbd, Cac...)
d. SPAD pixel photon detection probability model
establishment & simulation
2. Fab 2 Dtof SPAD pixel design
a. SPAD pixel layout design
b. SPAD pixel process simulation
c. SPAD pixel DC simulation (Vbd, Cac...)
d. SPAD pixel photon detection probability model establishment & simulation
e. SPAD pixel jitter model establishment & simulation
f. Improve CP yield to > 95% from < 50%
3. Optical finger print 4T pixel design
a. 4T pixel layout design
b. 4T pixel testkey design
b. 4T pixel process simulation
c. 4T pixel DC simulation (Vt, Vpin, Vpotential...)
d. 4T pixel transient simulation (FWC, lag...)
e. 4T pixel photo layer reduction (cost down)
Semiconductor :
1 Pixel layout design
2 Synopsis TCAD process simulation
3 Synopsis TCAD electrical & transient simulation
4 Semiconductor Physics and Devices
5 Semiconductor Process
Computer skill:
TCL, matlab, Word, Excel, PowerPoint
Interpersonal skill :
Communication, Teamwork Ability, Project Schedules Control
Language :
English : TOEIC 745 / 990