I-Shun Wang

Wafer level optics fabrication technology Implement and cleanroom flow planing and equipment layout configuration .

• Wafer level optics chips research and development:
• Improving metalens, grating and hole array structure (AR/VR optical component and biosensor) process (etching) in 12 inch glass wafer.
• Reduced garting structure CD range from 40 to < 20nm on glass structure
• Verified new etch tool based on procurement specifications.
• Built up off-line monitoring SOP to DL members before new tool connecting to overhead hoist transfer system.

• 1X nm DRAM periphery circuit layer process development and improvement
• Participated in products pilot run (4 times) and transferred to Fab manufacture team
• Fine tuned process parameters based on WAT and CP data analysis and requirement of process condition change.
• Process stability improvement: reduced 57% of gate oxide thickness range ; reduced 20% of gate width STD ; reduced 60% of gate Nitride THK range
• 6 Cpk item value improved from smaller than1.33 to larger than 1.67
• 6 Best Know Method reports in 2021(Total 62 reports drafted by 40 persons of division)