Jian-Lun Hong
Analog IC Designer
Overview
2
2
years of professional experience
Work History
Analog Design Engineer
MediaTek
01.2022 - Current
1. Multi-lane Tx integration for P2P/Vx1 interface applied to 75" 4K165 panel
2. Tx block design (e.g., cktree, ckgen, igen, serializer)
3. DP 1.4 HBR3
2. HDMI 2.0 Rx PLL design/integration in 16-nm node
Education
Master of Engineering - Electrical Engineering
National Tsing Hua University
Hsinchu, Taiwan 04.2001 -
Bachelor of Engineering - Engineering And System Science
National Tsing Hua University
Hsinchu, Taiwan 04.2001 -
Skills
Circuit Simulation/Analysis
Timeline
Analog Design Engineer
MediaTek
01.2022 - Current
Master of Engineering - Electrical Engineering
National Tsing Hua University
04.2001 -
Bachelor of Engineering - Engineering And System Science
National Tsing Hua University
04.2001 -