1. Multi-lane Tx integration for P2P/Vx1 interface applied to 75" 4K165 panel
2. Tx block design (e.g., cktree, ckgen, igen, serializer)
3. DP 1.4 HBR3
2. HDMI 2.0 Rx PLL design/integration in 16-nm node
Circuit Simulation/Analysis
Analog Design Engineer at INTEL | Capgemini EngineeringAnalog Design Engineer at INTEL | Capgemini Engineering
Analog Design Engineer at Anax Technology CorporationAnalog Design Engineer at Anax Technology Corporation
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Analog Design Engineer at MXICAnalog Design Engineer at MXIC