Summary

Overview

Work History

Education

Skills

Timeline

Liang-Yu Chen

Digital IC Design Enginee

Summary

Personal experience

◆ With project development experience in 3nm process & 4K monitor.

◆ 2yrs SerDes HDMI development experience and IP maintenance.

◆ 2yrs Block level integration & FPGA development and verification experience.

◆ International company cooperation experience - Samsung 、Sony

Overview

4

4

years of professional experience

2

2

years of post-secondary education

Work History

Research and Development Engineer

Mediatek

03.2020 - 01.2024

Responsible for SerDes digital (HDMI 2.1) interface. Understand Video & Audio interface and imaging and stream principles.

Has many years of experience in dealing with multiple clock domain crossing (CDC).

Can improve RTL that are easily caused timing issues by clock tree synthesis stage.

Ability to apply HDMI on FPGA and verify video & audio and pass CTS specification up to150MHz.

Familiar with Front-end related tools including Lint pre/post-simulation, timing analysis, power estimation, DFT and synthesis.

Identified and resolved critical issues during product development phases, ensuring timely project completion and customer satisfaction.

Set timelines and coordinated deliverables for R&D projects.

Optimized existing formulation and processes to improve product performance, process robustness and safety while reducing costs.

Managed multiple concurrent projects effectively, ensuring all deadlines were met and resources utilized efficiently

Education

Master of Science - Electrical Engineering

National Chung Cheng University

Chiayi

09.2017 - 11.2019

Skills

Image processing

Cost Reduction

Synthesis and formulation

Problem-Solving

Team Collaboration

Timeline

Research and Development Engineer

Mediatek

03.2020 - 01.2024

Master of Science - Electrical Engineering

National Chung Cheng University

09.2017 - 11.2019