Maricel (Macy) Sy
Kaohsiung City
Summary
To seek and maintain full-time position that offers professional challenges utilizing interpersonal skills, excellent time management and problem-solving skills.
Overview
18
18
years of professional experience
Work History
Package/Product Engineering Supervisor
Advanced Semiconductor Engineering
3 2014 - Current
- Key DRI for NPI/NPD for Flip Chip BGA, Automotive, MCM, CoWoS/2.5D
- Lead multiple external audits like ARR, PTR, TUV, VDA6.3, TS 16949
- Lead on APQP, Control Plan, FMEA, 8D and PPAP preparation
- Monitor product development life cycle and help customer post launch quality via failure analysis
- Worked with process and equipment engineering team to establish baseline, prepare equipment, tooling/fixtures needed to meet reliability, cost, yield, productivity and manufacturability
- Supervise overall project planning including timeline, schedules and risk assessment mitigations to ensure on time delivery of metrics and deliverables to customer
- Provide guidance, training and supervision to associate engineers
- Resolved conflicts among team members promptly, maintaining a harmonious working environment conducive to productivity.
- Established performance metrics for the team, consistently tracking progress towards goals and making adjustments as needed.
- Facilitated collaboration between team members on projects requiring cross-functional expertise for successful outcomes.
- Generated reports detailing findings and recommendations.
- Cultivated strong relationships with key clients or stakeholders through consistent communication and excellent service delivery.
- Conducted performance evaluations for staff members, identifying areas of improvement and guiding professional development plans.
- Enhanced communication within the team by holding regular meetings and encouraging open dialogue among all members.
- Evaluated staff performance and provided coaching to address inefficiencies.
Post Test Process Engineer
Texas Instruments (Phil) Inc.
07.2006 - 03.2014
- Process SME; provided trainings and qualification on process specifications
- Generates manufacturing specifications, work instructions, FMEA and Control Plan
- Provided defect analysis, performed assessment and disposition on line issues
- Supported new material qualification and product development releases and changes
- Work/coordinated with other groups to resolve internal/external/customer issues
- Direct contribution to revenue and profit through executing major engineering programs which significantly improved Cost Weighted Assembly and Test Yield (CWATY), Machine Productivity, Cycle time, Process Controls and Customer Quality
- Dry Bake Optimization – 4 hours CT improvement
- Automated Package Visual Inspection – removed naked eye inspection by 100%
- Reduced Symbol Teaching Problem due to Exposed HS Dimple – improved machine utilization/SPPH by 18% and 652.8 sec capacity gain realization
- Standardized and Automate Post Test Jobspecs/Recipe Management System (RMS)/Machine Parameter Settings –eliminated manual parameter input
- PLCC Process Flow Simplification – removed manual transferring of units that translated to 25.2 mins CT improvement.
Encapsulation Process Engineer
Texas Instruments (Phil) Inc.
07.2006 - 07.2008
- TIPI Encapsulation Process SME; Team Leader on the resolution of following issues: FCBGA 18x18 Package Voiding and Die Crack
- Developed and designed new heat spreader design from SINGLE to DOUBLE DIMPLE
- Re-designed SUMITOMO machine heat spreader loader plate
- Converted process requirement from Manual Molding to Auto-molding
- FCBGA Delamination/Substrate Bulging Resolution: Implemented Plasma Cleaning process before encapsulation
- Defined optimum Plasma Window Time and Parameter
- Micro-star BGA Offcenter Issue
- Defined molding parameters that highly affects material Coefficient of Thermal Expansion (CTE) and established SPC
- UBGA (16x16) Coplanarity and Wire Defect Process Improvement
- Implemented 100sec cooling time to all 16H devices
- Resolved wiresweep and wire-wire issues through removal of preheat process in all filmed devices
- Co-owner, TIPI UBGA No-RJM program.
Education
Bachelor of Science in Electronics and Communications Engineering -
College of Engineering, Iloilo Science and Technology University
06.2001 - 4 2006
Skills
Minitab Statistical Software and Applications
JMP Statistical Software and Applications
Measurement System Analysis (MSA)
8D/CAPA Methodology, FMEA, DMAIC, 7QC Tools, Control Plan
Project Management
Data Analysis and Problem-Solving
Self Motivated and Goal-Oriented
Attention to Details
Adaptability and Flexibility
Decision-Making
Technical Papers
- 18x18 Overmolded Flipchip Void Resolution through New Heat Spreader Design: The Double Dimple, 16th TIPI Technical Symposium
- Integrating Plasma Cleaning Process prior Encapsulation to Address Delamination/Bulging Issue on FCBGA Overmolded, 16th TIPI Technical Symposium
- Utilization of Chart Quality Metric of the Statistical Factory Control: PowerpadTM Stand-off Process Capability Improvement, 18th TIPI Technical Symposium
- Standardization of Dry Bake of Ball Grid Arrays through Moisture Diffusion Analysis, 18th TIPI Technical Symposium
- Revisiting Package VM Criteria – Turning Garbage to Gold, 18th TIPI Technical Symposium
- Understanding LIS/BIS Concept: Get Rid of Escapees and Customer Complaints, 20th TIPI Technical Symposium
References
- Zhijie (James) Wang, Senior Staff Package Engineer, Qualcomm, San Diego, 858-651-9747
- Sam Hu, Senior Staff PME, Qualcomm, Taiwan, (+886) 929-676-227
- Janea Celestial, Senior Account Manager, ASE US Inc. San Diego, 858-924-2138
Timeline
Post Test Process Engineer
Texas Instruments (Phil) Inc.
07.2006 - 03.2014
Encapsulation Process Engineer
Texas Instruments (Phil) Inc.
07.2006 - 07.2008
Bachelor of Science in Electronics and Communications Engineering -
College of Engineering, Iloilo Science and Technology University
06.2001 - 4 2006
Package/Product Engineering Supervisor
Advanced Semiconductor Engineering
3 2014 - Current