CUDA C Parallel Computing

Senior Engineer with 15 years of expertise in FPGA RTL design, kernel middleware, and GPU/NPU computing. Developed innovations in hardware-software co-design, including zero-copy image pipelines and deterministic FSM robotic controllers. Focused on embodied AI and edge computing, integrating advanced AI architectures with constrained SoC hardware. Leveraged Agilex 5 FPGAs and Jetson Thor platforms to create custom AVS pipelines, eliminating OS jitter and accelerating CV/ML inference at the edge.
Conducted integration of AI hardware and software for optimal performance.:
FPGA co-design
Edge AI solutions
GPU computing
AArch64 cross-compilation
Embedded firmware
CUDA C Parallel Computing
Edge AI Deployment
Vision Language Models (VLM) Integration
Computer Vision / Optical Flow
LLM Knowledge Engineering
Agentic AI Frameworks
AI-Driven HDL Generation
Hardware/Software Co-Design
FPGA & SoC Design (Verilog/RTL)
MCU Firmware Architecture
Linux Kernel & Device Drivers
High-Frequency Sensor Pipelines (
Digital Signal Processing (DSP)
Data Science / Python Automation/Data visualization
LLM Knowledge Engineering: Architecture design for adding domain-specific knowledge to Large Languag
CUDA C++ Parallel Computing: Applied GPU memory optimization, 1D/2D thread indexing (Grid/Block/War
LLM Knowledge Engineering: Architecture design for adding domain-specific knowledge to Large Languag