

IC Failure Analysis Engineer with 5+ years of hands-on experience in SEM-based physical failure analysis, delayering, and inline defect investigation. Adept at defining FA strategies, driving root cause analysis, and working cross-functionally to improve product quality and reliability. Seeking to leverage expertise to deliver impactful failure analysis and actionable insights in semiconductor R&D or manufacturing environments.
Failure Analysis: SEM, delayering, cross-section analysis, defect localization, IC sample preparation
Process Knowledge: FinFET, GaN HEMT, FEOL / MOL / BEOL fundamentals
Analysis Capability: Inline defect screening, PFA strategy definition, root cause analysis
Collaboration: Cross-functional communication, process and equipment coordination