Shao Chi Huang

• Designed and implemented sub-circuit IPs including Fast Wake-Up Bias, S&H Bandgap Reference, various OTAs/Transconductance Amplifiers, comparators, Auto-Calibration Zero-Cross Detection, and Refresher-Free N-N Driver.
• Developed control schemes for fast transient response and seamless mode transitions.
• Achieved 100 nA quiescent current in DCM mode, >90% power conversion efficiency across a 100,000× load range (10 µA–1 A), and maintained and maintained

HV LDO Design Project

• Circuit architecture optimization and performance verification.
• Reduced quiescent current by 50% and Ron by 7× while meeting strict PSRR, stability, and load transient specifications.
• Targeted overall performance to match industry benchmark (MAX25210), gaining hands-on experience in circuit design, simulation, and layout-aware analysis, demonstrating problem-solving and specification optimization skills.