Summary
Overview
Work History
Education
Skills
Accomplishments
Software
Interests
Timeline
Generic
Shih-Hsien Yeh

Shih-Hsien Yeh

Manager

Summary

Manage DRAM Engineering Group PE DFT (Design For Testing) team , leading the team to support yield enhancement , baseline quality maintenance, new coverage development across wafer /component and module level .

Overview

16
16
years of professional experience
2
2
years of post-secondary education
2
2
Languages

Work History

Manager - Compute DRAM PE DFT

Micron Technology, Inc
Taichung
05.2022 - Current

Team :

  • Size : 20+
  • Direct report : 3


Role :

  • NPI/HVM DFT ownership.
  • Maintained professional, organized, and safe environment for employees and patrons.
  • Established performance goals for employees and provided feedback on methods for reaching those milestones.
  • Maximized performance by monitoring daily activities and mentoring team members.
  • Managed and motivated employees to be productive and engaged in work.
  • Monitored and analyzed business performance to identify areas of improvement and make necessary adjustments.


Achievement :

  • 1 beta 32Gb DFT DDR5 DFT ownership, qual capable flow ready ~3month ahead.
  • 1 alpha 16Gb DDR4 DFT ownership , support PDTL team to hit mature yield target , best in class quality and 30+hours test time reduction.

Lead Product Engineer - Compute DRAM PE DFT

Micron Technology, Inc
Taichung
12.2019 - 05.2022

Team :

  • Size : 15
  • Direct report : 3


DDR4 NPI, role:

  • Test flow verification/development during Pre/Post Silicon phase.
  • Qualification capable flow driving/developing, across Probe/Burn/ATE/Module step ( wafer/component and module level test) .
  • Qual champion, develop test coverage and driving it to manufacturing test flow.
  • Optimize manufacturing test flow for yield ramp up while maintaining quality requirement to support PDTL moving new product to HVM phase.


DDR4 HVM sustaining, role:

  • Optimize manufacturing test flow based on customer feedback(RMA) to maintain baseline quality requirement .
  • Supported PDTL to ramp yield and continuous quality improvement to hit mature yield/quality target.


Achievement :

  • Lead TWN DFT team to support 4 HVM products(Pre-1 alpha) and successfully achieve mature yield target and best in class quality target.
  • Leading TWN DFT team for DFT ownership(first-ever) of 1 alpha 16Gb product and support PDTL team to achieve qualification milestone.

Lead Product Engineer - Compute DRAM Burn PE DFT

Micron Technology, Inc
Taichung
07.2017 - 12.2019

Team :

  • Size : 4.


DDR4 HVM sustaining (Burn flow), role:

  • Optimize manufacturing test flow based on customer feedback(RMA) to maintain baseline quality requirement .
  • Supported PDTL to ramp yield and continuous quality improvement to hit mature yield/quality target.


Achievement :

  • Build new hire training program for Burn DFT.
  • Continuous engineering capability improvement and start collaborate with GQ team to involve RMA cases.

Product Engineer - Compute DRAM Burn PE DFT

Micron Technology, Inc
Taichung
12.2016 - 07.2017

DDR4 HVM sustaining, role as following :

  • Manufacturing test flow maintenance/alignment, across product family.
  • Test flow optimization and driving manufacturing team for coverage deployment to support product team to achieve mature yield target.


Achievement :

  • Successfully build-up Burn DFT capability in TWN and take over DDR4 HVM product ownership from headquarter within a year.

Senior Product Engineer

Winbond Electronics Corp
Hsinchu
01.2012 - 12.2016
  • Product : SDR&DDR3
  • Driving improvement action across different functional team in order to achieve project milestone.
  • Design verification, report design weakness and co-work with Design team for design edit.
  • Wafer/Component level yield improvement.
  • Qualification failure analysis and improvement.

Product Engineer

Winbond Electronics Corp
Hsinchu
01.2008 - 01.2012
  • Product : GDDR3&DDR3
  • Design verification, report design weakness and co-work with Design team for design edit.
  • Wafer/Component level yield improvement.
  • Drive outsourced assembly and test house in Portugal( former Qimonda) to fulfill project milestone .

Education

Master of Science - Electrical Engineering

National Chung Hsing University
Taichung, Taiwan
08.2006 - 08.2008

Skills

    Staff Management

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Accomplishments

    Servant leadership

  • Growth and development
  • Empathy
  • Listening

Software

JMP

UNIX

Office Timeline

Interests

Hiking

Camping

Cooking

Timeline

Manager - Compute DRAM PE DFT

Micron Technology, Inc
05.2022 - Current

Lead Product Engineer - Compute DRAM PE DFT

Micron Technology, Inc
12.2019 - 05.2022

Lead Product Engineer - Compute DRAM Burn PE DFT

Micron Technology, Inc
07.2017 - 12.2019

Product Engineer - Compute DRAM Burn PE DFT

Micron Technology, Inc
12.2016 - 07.2017

Senior Product Engineer

Winbond Electronics Corp
01.2012 - 12.2016

Product Engineer

Winbond Electronics Corp
01.2008 - 01.2012

Master of Science - Electrical Engineering

National Chung Hsing University
08.2006 - 08.2008
Shih-Hsien YehManager