Summary
Overview
Work History
Education
Skills
Timeline
Generic
Swati Jha

Swati Jha

Tapeout Process, Integration And Yield
Bangalore

Summary

Thorough team contributor with strong organizational capabilities. Experienced in handling numerous projects at once while ensuring accuracy. Effective at prioritizing tasks and meeting deadlines.

Overview

12
12
years of professional experience
6
6
years of post-secondary education
3
3
Languages

Work History

Tapeout and Integration Engineer

TATA Semiconductor Pvt Ltd
11.2024 - Current
  • Part of seed team for technology transfer at PSMC, Taiwan in collaboration with TATA Semiconductor Ltd.
  • Leading mask ordering and tapeout process flow.
  • NTO: Test-Chips and complete Full-Chip GDS to mask and wafer start cycle.

Tape out Center (Member of Technical Staff)

Global Foundries
07.2019 - 11.2024
  • Responsible Design to Final Product (D2P) for 200-mm and 300-mm wafer size.
  • Collaborated closely with customer and cross-functional teams for successful product launches, ensuring seamless integration of new features and maintaining KPIs, increasing customer satisfaction by reducing cycle time and error rate.
  • Lead the daily operations supporting all Test-chip, MPWs, Product Tape-outs and Global Shuttles and Silicon Photonics technologies for APAC, EMEA, US Fabs.
  • Manage NPI lifecycle.
  • Leading team of 13 tapeout engineers.
  • Doing final verification run on completed layouts using Cadence and Assura software and MEBES checks before releasing final MASK to WRITE
  • Worked and involved in FMEA, 8D, structure problem solving to ensure timely and high quality tapeouts.
  • Working on Si/SiC/SiN/SiGe and Gallium Nitride (GaN) based various technologies
  • Working as Technical Program Manager (TPM) to EMEA customers and supporting pre fab sales.

Process, R n D Engineer

Saint Gobain
07.2018 - 06.2019
  • Responsible for different types of magnetrons sputtering coating done on Glass
  • In charge of in-line 84 Chambers long CVD coating process
  • Selection of material and in line process optimization for nano coating on glass to improve their yield
  • New product development and in-line testing
  • Collaborate and interact with Sales, Marketing, RnD, Chemical, Material and others stakeholders
  • Leading 11 people working in various production shifts.

Material Engineer

ERP Techconsultants
03.2015 - 06.2016
  • Selecting, developing and improving material for next generation consumer electronics goods
  • Responsible for identifying primary causes of failure and implementing corrective actions based on root cause analysis of any contributory factors
  • Working closely with the assembly team to design, fabricate and document reports
  • Applied core engineering principles when working through manufacturing processes.

Senior Project Fellow

CSIR-NPL
07.2014 - 03.2015
  • I effectively achieved the fabrication of thin film coating of BN (Boron Nitride) up to 5 nm on ferrous materials by PLD (Pulse Laser Deposition) and sputtering techniques and characterize them for Spintronic based nanodevices and nanosensors using techniques such as AFM, STM, XRD
  • Worked on designing and implementing circuit materials for spintronic device, data acquisition and control functions on silicon as a base material
  • Responsible for equipment testing and calibration to ensure compliance
  • Analyzed data and provided recommendations which resulted in the adoption of new cost-saving equipment.

Researcher in R&D

Veneto Nanotech
05.2013 - 11.2013
  • Simulated the structure and shape of nano antennas using FEM model analysis
  • Created GSD II structure using CAD for fabrication
  • I designed and fabricated unique structure of gold nano-antennas for 1000- 1600 cm-1 of Raman wavelength showing double resonance characteristics, that is having wide range of applications in lab on chip for making label free medicines, cancer detections and wireless technologies
  • I was working on tribology of nano-materials & surfaces that would enable selection of right chemistry of materials & coatings/deposition under specific operating environments through sputtering, electo-deposition techniques, SEM, XRD, STM and AFM
  • I was responsible for EBL fabrication and resolve proximity correction and photo-resist etching issues

Education

M.S. - Material Engineering and Nanotechnology

Politecnico di Milano
01.2011 - 01.2013

B.E. - Electronics and Communication Engineering

Maharshi Dayanand University
01.2006 - 01.2010

Skills

DRC/LVS/OPC Checks

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Timeline

Tapeout and Integration Engineer

TATA Semiconductor Pvt Ltd
11.2024 - Current

Tape out Center (Member of Technical Staff)

Global Foundries
07.2019 - 11.2024

Process, R n D Engineer

Saint Gobain
07.2018 - 06.2019

Material Engineer

ERP Techconsultants
03.2015 - 06.2016

Senior Project Fellow

CSIR-NPL
07.2014 - 03.2015

Researcher in R&D

Veneto Nanotech
05.2013 - 11.2013

M.S. - Material Engineering and Nanotechnology

Politecnico di Milano
01.2011 - 01.2013

B.E. - Electronics and Communication Engineering

Maharshi Dayanand University
01.2006 - 01.2010

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