林禹彤 Tony Lin

Analog Layout Design Engineer with a proven track record at CHENG HSIANG TECHNOLOGY LIMITED and TSMC, enhancing design efficiency and solving complex routing challenges. Skilled in layout optimization and teamwork, I've significantly contributed to projects like A14 and ACTB, showcasing robust design verification and exceptional customer service.

Experienced with analog layout design, focusing on creating efficient and high-performing integrated circuits. Utilizes precision and analytical skills to optimize layouts and ensure compliance with design rules. Strong understanding of collaboration and adaptability, supporting team success and project completion within deadlines.

Professional with strong background in analog layout design. Adept at creating and optimizing circuit layouts, ensuring precision and functionality. Proven ability to collaborate effectively in team environments and adapt to changing project requirements. Skilled in CAD tools, circuit simulation, and DRC/LVS verification, with focus on delivering high-quality results. Reliable team player known for achieving project milestones and contributing to innovative solutions.

After completing my training at the Tze Chiang Foundation of Science and Technology, I joined Cheng Hsiang Technology Limited as an IC Layout Engineer, where I was responsible for the layout design of analog and mixed-signal circuits. During my tenure, I primarily used Cadence Virtuoso, Calibre, and IC Validator for layout design and verification, and I am proficient in physical verification processes such as DRC, LVS, and ERC.

In my work, I have participated in the layout design of high-precision ADCs, LDO power management ICs, PLLs, and other circuits. Throughout the layout process, I placed a strong emphasis on matching (Matching), parasitic effect control (Parasitics), and routing optimization, ensuring that circuit performance is fully optimized. I also worked closely with design engineers, making layout modifications and optimizations based on circuit requirements and participating in the tape-out process to ensure that the final IC product complies with manufacturing specifications and design requirements.

Additionally, to enhance my technical expertise, I continuously study FinFET and TSMC advanced process (such as 5nm/7nm) layout guidelines and am currently pursuing a Master’s degree in Electrical Engineering to stay updated with the latest industry trends and best layout practices.

My experience in IC layout design has reinforced my passion and dedication to this field. I am highly motivated by the challenges of circuit layout and enjoy delving into optimization strategies to enhance circuit performance and product reliability. As semiconductor technology continues to advance, layout requirements for advanced processes have become increasingly demanding. This drives me to continuously learn and refine my skills to tackle the challenges presented by next-generation process nodes.

In the future, I aim to leverage my professional skills and accumulated experience to help the company overcome various layout design challenges, improve design quality, and enhance product performance. I am committed to accurately estimating layout timelines, optimizing workflows, and maximizing my efficiency to ensure projects remain on schedule. Furthermore, I look forward to collaborating closely with my team to enhance overall productivity, accelerate the design verification process, and create greater value for the company.