Wei Hao Kao
HsinChu,Taiwan
Summary
Highly skilled professional with extensive expertise in physical design and verification, utilizing tools such as Synopsys ICC2, FusionCompiler, DSO.ai, and Cadence Innovus. Proficient in physical verification using Mentor Calibre DRC and LVS, as well as Synopsys Primetime. Experienced in silicon to spice design and analysis with Synopsys HSPICE and Cadence Virtuoso. Adept at programming with Tcl-Tk. Committed to leveraging technical skills to drive innovation and efficiency in semiconductor design projects.
Innovative Application Engineer with knack for problem-solving and driving system improvements. Delivered key software updates that enhanced user experience and reduced downtime. Focused on collaboration and streamlined project workflows to achieve operational goals efficiently.
Overview
12
12
years of professional experience
7
7
years of post-secondary education
1
1
Certification
Work history
Sr. Staff Application Engineer
Synopsys
HsinChu
12.2018 - 12.2024
- - MediaTek R2G (RTL to GDSII) Strategy account engagement and project support
- - MediaTek SOC methodology development for advanced node (7nm~2nm)
- - Technical lead of Fusion Compiler / IC Compiler II for Tier-1 strategy account
- - Cooperate with MediaTek to develop Dimensity 7000 (6nm) and Dimensity 9000 (3nm) family
- - Win MediaTek 2nm Benchmark and led to deployment of Synopsys’ digital flow for MTK 2nm testchip
- Enhanced user experience by providing timely and effective support.
- Offered training on new software to customers for better understanding.
- Designed new applications, ensuring compatibility with existing systems.
- Met project goals by working cohesively with design and marketing teams to drive results.
Senior Engineer
Taiwan Semiconductor Manufacturing Company
HsinChu, Taiwan
01.2013 - 11.2018
- - DTP (Design Technology and Platform) physical design engineer to support tsmc advanced node process development through test chips
- - S2S (silicon to spice) analysis for process defeat diagnosis
- - Physical design service for Apple
- - Successfully tapeout 20+ test chips with advanced process node (16nm~5nm)
- - Cooperate with Apple to develop M series SOC chips (5nm)
- Developed and optimized physical design methodologies by using relevant software tools.
Education
Master's degree - Integrated Circuits & Systems
National Taiwan University
09.2009 - 06.2012
Bachelor's degree - Electrical and Electronics Engineering
National Central University
09.2005 - 06.2009
Skills
- Physical Design - Synopsys IC-Compiler II
- Physical Design - Synopsys FusionCompiler
- Physical Design - Synopsys DSOai
- Physical Design - Cadence Innovus
- Physical Verification - Mentor Calibre DRC
- Physical Verification - Mentor Calibre LVS
- Physical Verification - Synopsys Primetime
- Silicon to Spice design & analysis - Synopsys HSPICE
- Silicon to Spice design & analysis - Cadence Virtuoso
- Programming - Tcl-Tk
Accomplishments
2024 - Synopsys Best AE of 2H FY24.
2023 – Synopsys Taiwan Individual Contributor Award of Q4 FY23.
2016 - tsmc DTP Procedure Innovation Award
Certification
Papers
- S.-H. Hung, W.-H. Kao, K.-I W, Y.-W. Huang, M.-H. Hsieh, C.-P. Chen. “A
160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique”
IEEE International Symposium on Circuits and Systems (ISCAS), 24-27 May
2015.
Patterns
- US8937512B1.
- US20150214288A1
- US9117796B2
- US20180152178A1
- US10277206B2
- TW201539659A
Timeline
Sr. Staff Application Engineer
Synopsys
12.2018 - 12.2024
Senior Engineer
Taiwan Semiconductor Manufacturing Company
01.2013 - 11.2018
Master's degree - Integrated Circuits & Systems
National Taiwan University
09.2009 - 06.2012
Bachelor's degree - Electrical and Electronics Engineering
National Central University
09.2005 - 06.2009
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