Will Jan
Memory Designer
Hsinchu,Taiwan
Summary
To seek for a semiconductor business which can utilize my various memory IC design (SRAM/ DRAM/ NOR Flash) and project management experience. Hardworking memory designer skilled at building and maintaining positive relationships with test team and product team to bring memory chips to mass production. Top-notch attention to detail and problem-solving abilities with a resourceful mindset and thorough approach. Ready to apply 20 years of experience to a demanding long-term position.
Overview
21
21
years of professional experience
Work History
Project Director
Attopsemi Technology
Hsinchu, Taiwan
05.2021 - Current
- High density OTP memory IPs, test chips design.
- VIS 110nm, DBHiTech 130nm & UMC110nm Low power OTP IP design TSMC 55nm ULP.
09.2019 - 05.2021
- InferGen Tech, AI chip company founding and circuit design/ PIM design consulting.
Technical Deputy Director
FS-Semi Co., Ltd
Jupei, Taiwan
05.2015 - 08.2019
- Led a 5 men team to develop non-volatile memory products.
- 256kb nvSRAM, 1Mb/8Mb SPI and parallel NOR Flash chip using UMC110nm
- 4Mb SPI NOR flash chip using UMC 55nm
Deputy Director
eveRAM Technology
Hsinchu, Taiwan
06.2013 - 05.2015
- DRAM circuit Design & layout team management.
- 4Gb LPDDR2, LPDDR3 & LPDDR+ DRAM design using Nanya 30nm process.
Sr. DRAM design Manager
Elite Semiconductor Memory Technology Inc
Hsinchu
11.2006 - 12.2012
- 32Mb 2.3~3.6V wide range pSRAM using the 0.11um NTC trench DRAM processes.
- 16Mb\8Mb 2.3~3.6V wide range pSRAM using the 99nm NTC trench DRAM processes.
- 32Mb 3V pSRAM, 3V/1.8V pSRAM\ CellularRAM using the 90nm PSC stack DRAM process.
- 128Mb 3V/2.5V/1.8V x32/x16 Mobile DDR\SDR SDRAM using the 68nm PSC stack DRAM process.
- 256Mb 3V/2.5V/1.8V x32/x16 Mobile DDR\SDR SDRAM using the 63nm PSC stack DRAM process.
- 64Mb 1.8V ADMUX/AADMUX x16 CellularRAM using the 63nm PSC stack DRAM process.
- 1Gb x16 DDR2 SDRAM using the 38nm PSC stack DRAM process.
- 512Mb 1.8V x32/x16 MobileDDR SDRAM using the 45nm PSC stack DRAM process.
- DRAM related Patents CN103514942A/B Co-Inventor Circuit and method used for controlling leakage current in random access memory element.
Assistant professor
I-Shou University
Kaohsiung, Taiwan
02.2004 - 01.2007
- Advising and researching: Advised 2 MS theses about CMOS charge pumps design & SRAM sense amplifier design.
- Teaching: provided classes about microprocessor system, microelectronics, CMOS VLSI circuit design, probability, engineering mathematics, computer architecture, Verilog Hardware modeling, and discrete-time signal processing (DSP).
Sr. Design Engineer
Sony Electronics Inc
San Jose, CA.
10.2000 - 01.2003
- 16Mb Synchronous SRAM design, TSMC 0.18um logic process.
- 16Mb Synchronous SRAM design, TSMC 0.13um logic process.
Design engineer
ITEUSA Inc
Sunnyvale, CA.
04.1999 - 10.2000
- 16x16 multiplier design, MMC controller IP integration.
- SOC (186 + embedded DRAM) GPIOs, real-time counter, watchdog timer, AD\DA control circuit design.
Education
Ph.D - Electrical Engineering
Ohio University
M.S - Electrical Engineering
Ohio University
BS - Electrical Engineering
National Cheng Kung University
Skills
Memory circuit design
Tools: MatLab, HSPICE, Spectre, XA, AFS, NC-Verilog, Calibre, Virtuoso
Timeline
Project Director
Attopsemi Technology
05.2021 - Current
09.2019 - 05.2021
Technical Deputy Director
FS-Semi Co., Ltd
05.2015 - 08.2019
Deputy Director
eveRAM Technology
06.2013 - 05.2015
Sr. DRAM design Manager
Elite Semiconductor Memory Technology Inc
11.2006 - 12.2012
Assistant professor
I-Shou University
02.2004 - 01.2007
Sr. Design Engineer
Sony Electronics Inc
10.2000 - 01.2003
Design engineer
ITEUSA Inc
04.1999 - 10.2000
Ph.D - Electrical Engineering
Ohio University
M.S - Electrical Engineering
Ohio University
BS - Electrical Engineering
National Cheng Kung University