Yi-Hao Weng

I am Yi-Hao Weng, a CPU Verification Engineer at SiFive, with hands-on experience in CPU and cache verification using SystemVerilog and UVM. I am currently responsible for maintaining and enhancing cache-related testbenches, ensuring functional correctness and robustness of CPU designs.

I hold a Master’s degree in Electrical Engineering from National Chiao Tung University. Since the second year of my master’s program, I have been working at SiFive, initially as a CPU Verification Intern, where I built a solid foundation in UVM methodology and SystemVerilog-based verification. Through this role, I have gained practical experience in verification flow development, debugging, and collaborative work in a fast-paced CPU design environment.