YI KAI CHAN

Spearheaded 3 projects delivering quantified results, advancing TSMC’s R&D development.

• Enhanced OPC modeling SEM recipe robustness based on CD-SEM methodology, improving image quality by 19% and defect detection by 25%.
• Own wafer-edge improvement project to mitigate edge etch nonuniformity and yield from 146 to 148.5 mm.
• Optimized processes, cutting surface potential issues by 58% and boosting precision.

Led 2 projects for R&D product line transfer and methodology implementation through team cooperation.

• Led a 50+ member team to establish and transfer N2/A14 metrology product lines, integrating diverse expertise to execute advanced process initiatives.
• Collaborated with vendors and process teams to implement new advanced metrology tools (CD-SEM/AFM), boosting throughput by 20% and resolution by 23%.

Interface to Integrate automation and system improvements:

• Built SEM-image libraries for advanced High NA EUV nodes, enhancing hardware tuning knob.
• Created productivity automated mode, saving 8 hours of manpower daily.

• Developed an image processing index for HVM fabs (N16-N7), integrating sharpness, contrast, and noise metrics with trend chart analytics, cutting pattern variability by 18% and boosting defect detection by 22%.
• Collaborated with Advanced Quality teams to implement a next-generation inline QC system, enhancing real-time metrology control, saving NT$620M and reducing monitoring by 50%.
• Built an all-in-one automation reporting platform using VBA/JMP, deployed standardizing auto-chart.

• Engineered an automatic etch tuning solution, significantly improving optimization with TSMC TAP.
• Established automated metrology calibration, improving Feedback/Feedforward calibration workflow deviation by 36%, leveraging inter-layer feedback for enhanced process consistency.