Yi-Rui Chen
Staff Analog/Mixed Signal Engineer
Hsinchu
Summary
Staff Analog Mixed-Signal Design Engineer with extensive experience specializing in high-speed TRX and coherent SERDES architectures for next-generation data centers and optical communications. Expertise lies in clean-sheet design and re-architecting critical high-speed blocks to push the physical limits of advanced process nodes (2nm GAA& 3nm FinFET). Driven by the challenge of defining "from scratch" architectures and bridging the gap between theoretical circuit limits and silicon-proven reality.
Overview
6
6
years of professional experience
1
1
Language
Work History
Staff Analog Mixed-Signal Design Engineer
Nokia (formerly Infinera)
01.2023 - Current
- Next-Gen 1.6T (448G PAM4 equivalent) in 2nm: Driving architectural definition and full-custom implementation of 1.6T transceivers in TSMC 2nm, targeting specifications that surpass current 448G standards.
- Silicon-Proven 800G (224G PAM4) in 3nm: Led ground-up design of high-speed AMS blocks; achieved first-pass silicon success in 3nm FinFET meeting Tier-1 industry standards.
- RX TIADC & SAR ADC Innovation: Re-engineered RX sampling network (3-stage to 2-stage) to optimize bandwidth; doubled SAR ADC sampling rate from 600MS/s to 1.2GS/s.
- Transistor-Level Clocking: Developed full-custom RX/TX Clock Generators from scratch, ensuring ultra-low jitter performance for multi-channel high-speed sampling.
Analog Circuit Design Engineer
Airoha Technology Corp.
01.2020 - 01.2023
- ADC Optimization & Modeling: Improved Bluetooth/GPS RXADC power efficiency and speed; developed MATLAB/Simulink models for noise analysis.
- High-Speed Front-End: Contributed to CTLE design and measurement for Ethernet and various communication projects.
Education
Master of Science - Electrical Engineering (Analog Circuit Design)
National Tsing Hua University
Hsinchu, Taiwan01.2020
Bachelor of Science - Engineering and System Science (Electrical Group)
National Tsing Hua University
Hsinchu, Taiwan01.2017
Skills
Core Specialties: High-speed SerDes (800G & 16T), TIADC, SAR ADC, DAC, Clock Generation, AMS Modeling (Verilog-A)
Process Nodes: TSMC 2nm, 3nm, 7nm, 12nm,GAA/FinFET/CMOS
Design Tools: Cadence Virtuoso, Hspice, EMX, MATLAB / Simulink (Behavioral Modeling)
Timeline
Staff Analog Mixed-Signal Design Engineer
Nokia (formerly Infinera)
01.2023 - Current
Analog Circuit Design Engineer
Airoha Technology Corp.
01.2020 - 01.2023
Master of Science - Electrical Engineering (Analog Circuit Design)
National Tsing Hua University
Bachelor of Science - Engineering and System Science (Electrical Group)
National Tsing Hua University