Identified the specific equipment requiring parameter adjustments and collaborated with process engineers to implement the necessary changes, successfully restoring the yield from 80% to 95%
The issue of poor electrical performance at the wafer edges was investigated through thickness measurements, revealing an uneven thickness distribution
Conducted DOE to identify the problematic process step and successfully implemented improvements
Handled customer inquiries regarding product performance issues, drawing on process engineering expertise to provide timely and accurate resolution.
Conducted root cause analyses to identify underlying issues contributing to process variability, enabling targeted corrective actions that improved overall stability.
Optimized overlay alignment by working with photolithography engineers, implementing process adjustments that contributed to 8% yield improvement.
Process Integration Engineer – Intern
Taiwan Semiconductor Manufacturing Co. Ltd.
07.2021 - 09.2021
Participated in troubleshooting a product issue caused by insufficient electroplating voltage, which led to deposition voids
Collected and analyzed data, compiled reports, and contributed to identifying the root cause and improvement strategies
Education
Master of Science - Materials Science and Engineering
National Tsing Hua University
Hsinchu City, Taiwan
09.2020 - 08.2022
Bachelor of Science - Materials Science And Engineering
National Cheng Kung University
Tainan City, Taiwan
09.2016 - 07.2020
Software
PowerPoint
Excel
Python
Timeline
Process Integration Engineer
Powerchip Semiconductor Manufacturing Co. Ltd.
10.2023 - 04.2024
Process Integration Engineer – Intern
Taiwan Semiconductor Manufacturing Co. Ltd.
07.2021 - 09.2021
Master of Science - Materials Science and Engineering
National Tsing Hua University
09.2020 - 08.2022
Bachelor of Science - Materials Science And Engineering