Summary
Overview
Work History
Education
Skills
Area Of Expertise
Certifications Training
Autobiography
Personal Information
Timeline
Generic
Ying Chih Wu

Ying Chih Wu

可靠度實驗室
Kaohsiung

Summary

I majored in the Electrical or Electronic Engineering from bachelor to PhD and bring good research and development to get track in jobs well. And have 25-years working experience in the fields of assembly engineering, IC testing, product qualification, reliability tests, failure analysis and Lab management. During be a BGA engineering team leader, I need to perform the troubleshooting and define the strategy for production line. Any deviation or customer complain should be fixed immediately. Wide thinking, discussion to enhance the knowledge and information are very important before making the decision. Therefore, I maintain a positive and active learning attitude afterward. IC testing is another field, I plan to have full range know-how and technology at backend manufacturing. During the years of test engineer, I learned much experience on programming and PCB relation. And then applied my learning to improve test yield through material analysis on test socket and PCB board debug. 10 years working experience at backend support me to deal with problem on reliability successfully. I have 12 years working experience on package and board level reliability tests up to now. In NXP, I led a reliability team in PQC (Product Quality Center), define the roadmap and co-work with other sites (incl. Lab at Nijmegen, Austin, Tianjin). In Vishay, I am a division reliability & FA manager and work with 3 Labs in Shanghai, Kaohsiung and Manila. Substrate is a key and complicated material in package. In order to have deep learning on substrate. I go to Kinsus to be a senior manager and manage 4 reliability/FA Labs in Taiwan. And deal with intractable problem from customer. Currently, I lead 3 engineers and 207 technicians at Chemical and Surface Analysis Labs in TSMC. There are 12 Labs and throughout Hsinchu/Taichung/Tainan science industrial parks. I also support some engineering project in reliability Lab. My personalities are optimistic, thoughtful, easygoing, getting along with people easily and emphasize ethics. I love learning, and highly self-achievement. So I do my best in job, and getting fun from them. I do believe I am the best choice. I’ll desire to put all my learning, sharing and contribute all my strength and enthusiasm. It signifies a heartfelt anticipation of serving. Thanks for considering my application.

Overview

27
27
years of professional experience
14
14
years of post-secondary education

Work History

Section Manager

TSMC
03.2022 - Current
  • Lead 3 engineers and 153 technicians to perform chemical analysis on inputs of chemical materials and monitor contamination during Fab process or environment (incl. ICP-MS, AMC analysis, Ion Chromatography analysis), and 54 technicians for wafer surface analysis (incl TOF secondary-ion mass spectrometry).
  • Support engineering departments. Personal performance assessment. Promotion on Job grade and function. Personnel care and report on any abnormal issue. Man power management. SOP definition (incl. Safety appliances, chemical sorting and recycling).
  • Support new comer hiring. Foreign Labs at AZ and JASM have sent new comers to Taiwan for training and real practice.
  • B-HAST is a critical test in reliability Lab, due to spend much time on smell exhaust and PCB baking. I co-work with PCB supplier and engineering department to evaluate the optimum materials of test board and socket to avoid the extra processes.
  • Support to review and improve the ESD environment in Reliability Lab.

Senior Reliability and FA Manager

Kinsus Tech.
08.2020 - 03.2022
  • Product: FC-CSP and RF substrate for both 5G and Automotive application of advanced package.
  • Planning for new equipment investment, infrastructure, human request.
  • In order to keep all knowledge and experience. I built a report database to keep all FA and reliability reports in the system. Everyone can search related knowledge through this system.
  • Evaluate new instrument (eg. reflow equipment, bHAST) and any investment.
  • During new product development, we need to implement Shadow Moire to see the warpage behavior. Our Lab provide this technology and co-work with NPI department to improve warpage problem.
  • Kinsus Tech. often encounter substrate complaint from assembly house or end customer. CQE engineer is the contact window to deal with these issues. Currently, I played the role of consultant to reply customer’s question. And comment how to apply our reliability & FA approaches to find the root cause.

Division Reliability and FA Manager

Vishay Semiconductors MOSFET/IC Division
10.2018 - 08.2020
  • Product: IC and MOSFET on power/switch for both Automotive and commercial application.
  • Roadmap planning & implement reliability tests and re-qualification on automotive products.
  • Regular review reliability safe launch and monitoring, in-house & subcontractor, with statistical approach (incl. SYA, SYL, SBL). In case any critical deviation be found, we will organize the MRB (Material Review Board) & implement 8D procedure to find the root cause or FA evidence for improvement.
  • Follow the strategy and provide regular update on MPE (Maverick Product Elimination) & ORT (On-going Reliability Tests) with statistical data to specific customer.
  • Management on human resource, facility, infrastructure, equipment utilization and space.
  • Enhance capability and capacity of reliability and FA Labs.
  • Evaluate new instrument (eg. PVA SCAT, BLR & WLR tester) and any investment.
  • Balance human and capacity loading among Labs (incl. Shanghai, Kaohsiung, Manila and San Jose).
  • Co-work with R&D during the product development phase by ANSYS.
  • Coordinate internal activities to solve customer problem & issue.

Team leader in Product Quality Center

NXP/Philips Semiconductors
08.2004 - 09.2018
  • Reliability engineering: Product lifetime, qualification strategy, test approaches, structure similarity.
  • Create qualification plan and pass review board.
  • Failure analysis & improvement by 8D/PDCA/DMAIC.
  • Risk assessment before project launch.
  • Host BIT (Business Improving Team) and applied QC tools: I led the teams and applied QC tools to win the good achievement in 2010 & 2016.
  • Made road map for BLR development.
  • Evaluate materials (incl. CTE, Young’s modulus, Poisson effect) for new product tests.
  • Establish database to perform structure similarity (incl. package/die dimension, SAC ball combination, materials/substrate/supplier, manufacturing).
  • SMT technology: Incl. fine tune thermal profile to solve large void, HIP, poor wetting, OSP/ENIG/IMC issue.
  • Evaluation on BLR thermal cycling, drop/shock, bending, vibration and TH-Dwell tests.
  • Perform Weibull analysis to support FA decision and reporting.

Research development test engineer

Pan Jit Semiconductor Corp.
06.2002 - 08.2004
  • Implement MOSFET tester and knowledge transfer from Japan TESEC.
  • Improve testing (incl. BJT, Triac, Thyristor, Zener, Schottky & diode).
  • Establish ESD environment in production line for component testing with oxide process.
  • Process improvement: Implement laser to instead of traditional marking.
  • Component reliability tests and Failure Analysis.

BGA engineering, team leader of molding process

OSE Semiconductor
07.1998 - 06.2002
  • Improve assembly yield on molding process.
  • Perform DoE to have optimum molding parameters (incl. plunger speed, final pressure, preheat, post mold cure, gel time).
  • Material evaluation: Test EMC viscosity by spiral flow.
  • Establish the environment for ESD protection.
  • Define the standard operation procedure.

Education

PhD - Electrical Engineering

National Cheng Kung University
Tainan, Taiwan
09.2012 - 12.2017

Master - Electronic Engineering

I-Shou University
Kaohsiung, Taiwan
09.2002 - 07.2004

Bachelor - Electronic Engineering

National Kaohsiung University of Applied Sciences
Kaohsiung, Taiwan
09.2000 - 07.2002

Associate degree - Electronic Engineering

Cheng Shiu University
Kaohsiung, Taiwan
09.1990 - 07.1995

Skills

  • Product Reliability
  • Qualification and Failure Analysis
  • Automotive product qualification
  • Reliability tests
  • Quality system adherence
  • Customer complaint handling
  • Design of Experiments (DOE)
  • Thermal cycling
  • ANASYS simulation
  • Project management
  • Reliability Data Acquired System (rDAS)
  • Failure Analysis
  • Electrical verification
  • Fault localization
  • Non-destructive testing
  • X-ray
  • SCAT
  • 3D OM
  • EMMI
  • OBIRCH
  • ELITE
  • TDR

Area Of Expertise

  • Product Reliability, Qualification and Failure Analysis
  • Package and Board Level Reliability Engineering
  • Assembly Engineering and IC Testing
  • Excellent Handling & Management on Customer Complaint

Certifications Training

  • High-speed signal transmission in PCB, 10/2021, FA, TPCA, Taoyuan
  • Destructive analysis and investigate intermetallic compound, 04/2021, FA, TPCA, Taoyuan
  • Green belt certification, 12/2017, Quality, NXP, Kaohsiung
  • Micro step training for problem solving, 07/2017, Quality, NXP, Kaohsiung
  • Wafer Fab process training, 07/2017, Fab process, NXP, Kaohsiung
  • BLR competence development, 11/2016, Reliability, NXP, Kaohsiung
  • ELITE (Enhanced Lock-In Thermography) certification, 01/2016, FA, NXP, Kaohsiung
  • WLCSP process training, 01/2015, Assembly, NXP, Kaohsiung
  • Advanced training on 'Board Level Reliability tests', 11/2013, Reliability, NXP, Netherlands
  • OHSAS18001 & ISO14001 auditor training, 05/2013, Quality, Kind, Kaohsiung

Autobiography

I majored in the Electrical or Electronic Engineering from bachelor to PhD and bring good research and development to get track in jobs well. And have 25-years working experience in the fields of assembly engineering, IC testing, product qualification, reliability tests, failure analysis and Lab management. During be a BGA engineering team leader, I need to perform the troubleshooting and define the strategy for production line. Any deviation or customer complain should be fixed immediately. Wide thinking, discussion to enhance the knowledge and information are very important before making the decision. Therefore, I maintain a positive and active learning attitude afterward. IC testing is another field, I plan to have full range know-how and technology at backend manufacturing. During the years of test engineer, I learned much experience on programming and PCB relation. And then applied my learning to improve test yield through material analysis on test socket and PCB board debug. 10 years working experience at backend support me to deal with problem on reliability successfully. I have 12 years working experience on package and board level reliability tests up to now. In NXP, I led a reliability team in PQC (Product Quality Center), define the roadmap and co-work with other sites (incl. Lab at Nijmegen, Austin, Tianjin). In Vishay, I am a division reliability & FA manager and work with 3 Labs in Shanghai, Kaohsiung and Manila. Substrate is a key and complicated material in package. In order to have deep learning on substrate. I go to Kinsus to be a senior manager and manage 4 reliability/FA Labs in Taiwan. And deal with intractable problem from customer. Currently, I lead 3 engineers and 207 technicians at Chemical and Surface Analysis Labs in TSMC. There are 12 Labs and throughout Hsinchu/Taichung/Tainan science industrial parks. I also support some engineering project in reliability Lab. My personalities are optimistic, thoughtful, easygoing, getting along with people easily and emphasize ethics. I love learning, and highly self-achievement. So I do my best in job, and getting fun from them. I do believe I am the best choice. I’ll desire to put all my learning, sharing and contribute all my strength and enthusiasm. It signifies a heartfelt anticipation of serving. Thanks for considering my application.

Personal Information

Age: 52

Timeline

Section Manager

TSMC
03.2022 - Current

Senior Reliability and FA Manager

Kinsus Tech.
08.2020 - 03.2022

Division Reliability and FA Manager

Vishay Semiconductors MOSFET/IC Division
10.2018 - 08.2020

PhD - Electrical Engineering

National Cheng Kung University
09.2012 - 12.2017

Team leader in Product Quality Center

NXP/Philips Semiconductors
08.2004 - 09.2018

Master - Electronic Engineering

I-Shou University
09.2002 - 07.2004

Research development test engineer

Pan Jit Semiconductor Corp.
06.2002 - 08.2004

Bachelor - Electronic Engineering

National Kaohsiung University of Applied Sciences
09.2000 - 07.2002

BGA engineering, team leader of molding process

OSE Semiconductor
07.1998 - 06.2002

Associate degree - Electronic Engineering

Cheng Shiu University
09.1990 - 07.1995
Ying Chih Wu可靠度實驗室