

Job Function
PFMEA/DFMEA of advance/traditional assembly package
3D Packaging (TSV) Process / Post Wafer Finishing Process (Bumping) know how
EFA/PFA Analysis in Assembly/BEOL/Device Level
Wafer Probe/Back end test software bin/hardware bin analysis
WAT (In-line/Final Param) data analysis
Layout review and pulling skill (K2 viewer/Cadence Virtuoso)
8D/KT Problem Solving
JMP, Linux/Unix, Git/Gitbucket
Backend Electrical Yield Analysis / In-line Data Analysis
Process Enhancement by DOE (Screen DOE, Factorial experiment)
Package reliability
Wire bond / Flip Chip / SiP assembly packaging process (L/F base and Substrate base)
APQP/NPI procedure complied with VDA63/IATF16949
Automotive package
6 Sigma Green Belt (Understanding to CpK/DMAIC flow and procedure)
Overseas Residing supporting experience at Sunnyvale (California Silicon Valley)
Substrate/Lead frame design and manufacturing flow
Demonstrated respect, friendliness and willingness to help wherever needed
Excellent communication skills, both verbal and written
Skilled at working independently and collaboratively in a team environment