Zhang ReiFu

Hardware Engineer(Architecture team) at Mediatek, specializing in ARM v9.4 CPU integration and FPGA prototyping to enhance & analyze CPU IP performance. Expert in RISC-V SoC architecture and multimedia digital circuit design. Proficient in C/C++ and scripting languages, Linux.

Bring up ARM P&Q Channel debugger IP with Verilog VCS environment , ensure CPU boot up with correct Power states transfer flow. Dramatically reduce debug time.

Setting UP a parsing flow IP to monitor ARM CPU's bandwidth and latency between NOC&EMI system , multi-core communication. Provide the team with a more detailed analysis of the performance of the processor's L1, L2, and L3 cache modules.

Use Chisel and Verilog to build up a RISC-V soc with 6&4 Out-Of-Order CPU system on Xilinx FPGAs,Booting Linux and running Dhrystone for      FPGA prototyping. Dhrystone Score is 4.132,smash ARM Cortex-M CPUs.

Bring up a multimedia system for Gowin FPGAs with Verilog,including UART&HDMI and SPI. The system required low Lut4 cost and easy to modify, all IP is controlled by a self-developed RISC-V in-order CPU and connect with AXI Bus.

To replace RaspberryPI in old system,I bring up FPGA Based Heterogeneous AI system with proprietary IO blocks on the PL side and integrating software on the PS side with PetaLinux, running C++ Yolov4 applications on MPSoC FPGA. Enhance system Image processing capabilities from 3fps to 24 fps.