Technical Manager
MEDIATEK INC,
HSINCHU, TW
02.2014 - Current
- Responsible for package design of integrated chip, include ball map arrangement, providing routing rule, and running PI/SI simulation of PKG to check performance.
- HW development of engineering platform for chip verification and system reference board for demo from 10G up to per lane 112G-pam4 Ethernet product.
- Handling flow and environment set-up for HTOL.
- Handling testing item and patterns of chip production.
- Worked with cross function teams to define product hardware
specifications, system verification. - High-Speed signal and timing clock jitter measurements and characterizations.
- Write datasheet and HW Design Guide of product.
- Schematic/Layout review, simulation report review and supporting system board debugging and TX FIR related tuning for ODM customers.
