Summary
Overview
Work History
Education
Skills
Software
Timeline
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Daniel Liu

Daniel Liu

IC Layout Engineer

Summary

My name is Daniel Liu, and I was born in Taoyuan in 1996. From a young age, I have had a strong interest in electronics and machinery. During my university years, I gradually became acquainted with IC layout, which sparked my deep interest in this field. After graduating, I entered the IC layout industry and have been working at Yu-Chih Information Co., Ltd. for over three years, frequently stationed at MediaTek. During this time, I have primarily been responsible for supporting departmental projects, including project sub-block layout, floorplan, top integration, IO ESD, standard cell, as well as DRC/LVS/ERC/ANT verification and debugging. I have had the opportunity to work with various processes, including TSMC's 2/3/5/7/12nm, UMC's 0.153um/22nm, and Intel's I16, which has given me a deeper understanding of various aspects of IC design. I believe my strengths include being personable and easy to get along with, as well as being responsible, diligent, and committed to doing my best in all tasks. I am eager for the opportunity to join your company, where I can leverage my skills and contribute to the team.

Overview

6
6
years of professional experience
2
2
Languages

Work History

IC Layout Engineer

Yu-Chih Information Co., Ltd.
10.2020 - Current


  • Stand cell - 0.5 years
  • LVSH (Public version) - 0.5 years Create multi bit version
  • Audio Codec- 1 years Marco & Whole chip support( ANATOP /CLASS-H/DNLINK experience)
  • UFS- 1 years Marco & Whole chip support(PLL integration)
  • DDR- 0.5 years(now ongoing) Marco & Whole chip integration

IC Layout Engineer

Silicon Topology
10.2018 - 10.2020
  • Sram- 2 years Marco & Compiler support

Education

Bachelor of Science - Optoelectronics & Materials Engineer

Chung Hua University
Hsinchu, Taiwan
04.2001 -

Skills

Independent execution and effective team leadership

Software

Virtuoso

Laker

Calibre

Customer Compiler

Timeline

IC Layout Engineer

Yu-Chih Information Co., Ltd.
10.2020 - Current

IC Layout Engineer

Silicon Topology
10.2018 - 10.2020

Bachelor of Science - Optoelectronics & Materials Engineer

Chung Hua University
04.2001 -
Daniel LiuIC Layout Engineer